1. Field of the Invention
Embodiments of the invention relate to the field of semiconductor devices, and more specifically, to testing of semiconductor devices.
2. Description of Related Art
Testing of semiconductors devices during manufacturing process is generally classified into two techniques: sequential test and parallel test. Parallel test usually offers cost saving in terms of testing time and capital equipment purchases. Most test techniques generate test data input (TDI) to a test access port (TAP) and interfaces to an automatic test equipment (ATE) devices.
There are assembled products that may not be efficiently tested using parallel test mode. Examples of these products include joined-at-bump cores or processor cores that do not have co-operative or shared circuit designs. Existing techniques to provide parallel test mode for these assembled products have a number of disadvantages. One technique uses a software mechanism to achieve parallel TDI signal delivery. This technique requires increased number of TAP instructions, increased TAP test time, increased ATE vector memory consumption, and increased simulation and design collateral complexity. Other techniques are unable to detect mid-band signals from multiple processors or multiple cores, and therefore have limited use in parallel test mode.